1. Field of the Invention
The present invention relates to a memory, and more particularly to the layout and the structure of a NAND flash memory.
2. Description of the Prior Art
Recently, as demands for the portable electronic devices are increasing, the market for the flash memory and the electrically erasable programmable read-only memory (EEPROM) is also expanding as well. The aforesaid portable electronic device includes the storage memory for the digital camera, the cell phones, the video game apparatuses, PDAs, telephone answering machines, and the programmable ICs, etc. A flash memory belongs to a non-volatile memory, and has an important characteristic of being able to store data in the memory even though the power is turned off. By changing the threshold voltage of the transistor, the gate can be turned on and off, and the data can be stored in the transistor. Generally speaking, the flash memory can be divided into two types of configurations, namely, a NOR flash memory and a NAND flash memory. The drains of memory cells of a NOR flash memory are connected in parallel for a faster reading speed, which is suitable for code flash memory mainly used for executing program codes. The drains and sources of two neighboring memory cells of a NAND flash memory are serially connected for integrating more memory cells per unit area, which is suitable for a data flash memory mainly used for data storage. Both of the NOR flash memory and the NAND flash memory have a MOS-like memory cell structure, so as to provide advantages of smaller size, higher operation speed, and higher density.
As the electronic device becomes smaller, integration of the flash memory needs to be increased. Therefore, it is an object of the present invention to provide a new layout and structure for the flash memory to increase the integration of the flash memory. The layout design according to the present invention can make the size of the flash memory smaller.